1. Field of the Invention
The present invention relates to a technique of adjusting a dot clock signal for processing a video signal. Especially the invention pertains to a technique of adjusting the phase of a dot clock signal as well as to a technique of adjusting the frequency of the dot clock signal. The video signal in the present invention denotes an image signal supplied from an image signal output device such as a personal computer.
2. Description of the Related Art
FIG. 40 is a block diagram illustrating a video image display apparatus utilizing a conventional technique. The video image display apparatus includes an A-D converter 1, a driving circuit 2, a display device 3, a display timing control circuit 5, a PLL (Phase Locked Loop) circuit 7, and a delay circuit 10. The PLL circuit 7 multiplies the frequency of a horizontal synchronizing signal 102 for an analog video signal 101, by a predetermined factor Nd to generate a reference clock signal 200. The delay circuit 10 gives a delay xcfx86 to the reference clock signal 200 to generate a dot clock 201. The analog video signal 101 is sampled by an A-D converter 1 at a rise of the dot clock 201 land converted to a digital video signal 110. The driving circuit 2 executes a signal processing on the digital video signal 110 to make it suitable for the display device 3, and supplies the processed video signal to the display device 3 for display of an image. The dot clock 201 is also given to the driving circuit 2, the display device 3, and the display timing control circuit 5. The display timing control circuit 5 further receives the horizontal synchronizing signal 102. The display timing control circuit 5 controls the display timing of the display device 3 according to the horizontal synchronizing signal 102 and the dot clock 201.
The PLL circuit 7 and the delay circuit 10 constitute a dot clock regeneration circuit for regenerating a dot clock signal (dot clock) suitable for the processing of the analog video signal 101, from the horizontal synchronizing signal 102. The factor Nd in the PLL circuit 7 and the delay xcfx86 in the delay circuit 10 are adjustable parameters in generating the dot clock 201. In other words, it is desirable to set appropriate values to both the delay xcfx86 and the factor Nd, in order to regenerate the dot clock signal suitable for the analog video signal 101. The delay xcfx86 of the dot clock signal relates to the phase of the dot clock signal, whereas the factor Nd relates to the frequency of the dot clock signal. There are some problems regarding the adjustment of the delay xcfx86 (that is, the adjustment of the phase) and the adjustment of the factor Nd (that is, the adjustment of the frequency) as described below.
The analog video signal 101 output from a video image output apparatus, such as a personal computer, was generated in synchronism with an internal video clock of the video image output apparatus. The signal level thus varies at the cycles of the internal video clock. A dot clock (also referred to a sampling clock) having the same frequency as that of the internal video clock of the video image output apparatus is required in order to carry out appropriate signal processing for displaying a video image corresponding to the analog video signal 101 on the display device 3 or the signal processing for writing the analog video signal 101 into a memory. In the computer system, such as a personal computer, however, no video clock is output to an output terminal of video signals. In the conventional system shown in FIG. 40, the PLL circuit 7 multiplies the frequency of the horizontal synchronizing signal 102 by the factor Nd to generate the reference clock signal 200, and the delay circuit 10 further gives a delay to the reference clock signal 200 to regenerate the dot clock 201. Here the factor Nd in the PLL circuit 7 is set to coincide with a demultiplication factor, or frequency division ratio, used for generating the horizontal synchronizing signal 102 from the video clock in the video image output apparatus. This makes the dot clock 201 to have the same frequency as that of the original video clock.
FIGS. 41(a)-41(c) are timing charts showing the relationship between the video signal 101 and the dot clock 201. The video signal 101 has a stable range 121 having image information proper to the video signal 101 and a transient range 122 including ringing and rounding generated by the effects of an output circuit of the video image output apparatus and a connection cable. When a dot clock rising in the stable range 121 such as a dot clock 201A shown in FIG. 41(b) is used, a normal video image is displayed on the display device 3. When a dot clock rising in the transient range 122 such as a dot clock 201B shown in FIG. 41(c) is used, on the other hand, the A-D converter 1 samples image information that is not proper to the video signal 101, and the resulting video image displayed on the display device 3 accordingly has undesirable noises or poor sharpness.
FIGS. 42(a)-42(c) are timing charts showing the relationship between the horizontal synchronizing signal 102, the reference clock 200, and the dot clock 201. The reference clock 200 output from the PLL circuit 7 is in phase with the horizontal synchronizing signal 102. Since the relationship between the phase of the horizontal synchronizing signal 102 and that of the video signal 101 is not specifically defined, the phase at a rise of the reference clock 200 may deviate from the phase of the video signal 101. A rise of the dot clock 201 may accordingly exist in the transient range 122 (FIG. 41(a)).
In the conventional system, a user manually adjusts the delay time xcfx86 (that is, the phase) of the dot clock 201 shown in FIG. 42(c) to an optimum state while checking a video image on the display device 3 so that the displayed video image has no noise and sufficient sharpness. This manual operation is, however, rather troublesome, and little understanding of the requirement for the adjustment may lead to some misunderstanding that the display device has poor performance or even malfunctions.
A method of automatically adjusting the phase of the dot clock 201 is, for example, disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 4-276791. This method comprises the steps of: sampling two sets of image data in synchronism with dot clocks having different phases; storing them into two different memories; and determining an optimum phase of the dot clock so that the two sets of image data read out of the memories coincide with each other. When the video signal includes ringing and rounding and has a narrow stable range, only a little shift of the phase causes a difference in the resulting image data. Potential noise also slightly changes the image data. The two sets of image data obtained with the dot clocks with different phases thus hardly coincide with each other actually, and it is rather difficult to determine the optimum phase of the dot clock. This method also requires two high-speed line memories to process high-speed video signals, thereby undesirably raising the equipment cost.
The adjustment of the factor Nd in the PLL circuit 7 (FIG. 40), that is, the adjustment of the frequency of the dot clock, also has the following problem. FIG. 43 shows timing of the video signal 101 in a two-dimensional manner. A standard video signal is a one-dimensional signal representing a video image on each scanning line. One page image is constructed by scanning each line from left to right in the horizontal direction and repeating the scanning procedure for all the lines in one page from an upper left end to a lower right end. A horizontal synchronizing signal 102 adjusts the scanning timing of the video signal 101 in the horizontal direction, whereas a vertical synchronizing signal 103 adjusts the scanning timing of the video signal 101 in the vertical direction. A CRT display requires a time period for returning the electron beam from right to left and from bottom to top, so that blanking areas 302 are set both in the horizontal direction and in the vertical direction. An effective signal area 301 other than the blanking area 302 is the area in which a video image is actually displayed. The timing of the blanking area 302 and the effective signal area 301 in the horizontal direction is expressed by the number of pixels corresponding to the number of pulses of the dot clock. Although the timing in the vertical direction should be expressed by the number of scanning lines, it is often expressed by the number of pixels instead.
In personal computers, there are several standard sizes for the effective signal area 301. Typical standards include VGA (640 pixels (dots) in the horizontal directionxc3x97480 pixels in the vertical direction), SVGA (800 pixelsxc3x97600 pixels), XGA (1024 pixelsxc3x97768 pixels), and SXGA (1280 pixelsxc3x971024 pixels). The specific standard applied to the video signal can be identified from the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal of the video signal.
These standard sizes represent the number of pixels included in the effective signal area 301 of FIG. 43 and do not define the total number of pixels in one scanning line including both the blanking area 302 and the effective signal area 301. A variety of arbitrary values are actually used as the total number of pixels for one line. While the number of pixels in the effective signal area 301 can be determined from the synchronizing signals, the total number of pixels for one line is unknown, and therefore the optimum factor Nd to be set in the PLL circuit is unknown.
FIGS. 44(a-1)-44(a-3) and FIGS. 44(b-1)-44(b-3) are timing charts showing the relationship between the analog video signal 101, the dot clock 201, and the digital video signal 110. The digital video signal 110 is shown in the analog form for the clarity of explanation. FIGS. 44(a-1) through 44(a-3) show the case in which the factor Nd in the PLL circuit 7 is equal to a frequency division ratio used for generating the horizontal synchronizing signal from the video clock in the video image output apparatus that generates the video signal 101. In this case, the phase of the dot clock 201 relative to the variation points of the video signal 101 is fixed. The resulting digital video signal 110 appropriately reproduces the video signal 101 and enables a proper video image to be displayed on the display device 3.
If the factor Nd in the PLL circuit 7 is different from the frequency division ratio in the video image output apparatus, on the other hand, the phase of the dot clock 201 relative to the video signal 101 varies with respect to each position in the horizontal direction as shown in FIGS. 44(b-1) through 44(b-3). In this case, the amplitude of the digital video signal 110 varies according to the pixel position, and thus shows xe2x80x9cbeatsxe2x80x9d. A resulting video image displayed on the display device 3 shows vertical lines due to the small amplitude portion of the beats and may suffer from a loss of some image information.
In the conventional video image display apparatus, appropriate factors Nd for the commercially-available popular personal computers may be registered in advance. The type of the video image output apparatus is identified according to the frequencies and the polarities of the horizontal synchronizing signal 102 and the vertical synchronizing signal 103. The optimum factor Nd for the video image output apparatus is then selected from the preset alternatives and set in the PLL circuit 7. In case that the appropriate factor Nd has not been registered for a specific video image output apparatus, the user has to manually set the optimum factor Nd while monitoring the screen of the display device.
Known methods for automatically determining the unknown factor Nd are, for example, disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 3-295367 and No. 5-66752.
The method disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 3-295367 stores the sampled video signals in a compressed form and checks whether or not the data are stable with respect to a plurality of inputs, thereby detecting a deviation of the factor.
This method only detects whether the factor is deviated or not, and cannot determine the degree of the deviation. This method would repeat the comparison while varying the factor and thus requires a relatively long time for determining the optimum factor. Further, if the phase of the dot clock (that is, the delay xcfx86 in the delay circuit 10) is improper, this conventional method cannot determine the optimum factor.
Another known method disclosed in JAPANESE PATENT LAID-OPEN GAZETTE No. 5-66752 detects a dot cycle from the edge component of the video signals: detects a scanning cycle from the horizontal synchronizing signal; and compares the dot cycle with the scanning cycle to determine the factor in the PLL circuit.
This method, however, requires another clock signal having a significantly higher frequency than that of the dot clock to measure the dot cycle. An extremely high dot clock frequency would be required for signals having a large total number of pixels. This method is accordingly not practical.
An object of the present invention is thus to provide a technique for appropriately adjusting a dot clock for video signals by a simple process.
The present invention is directed to a method of adjusting a phase of a dot clock signal for a video signal. The method comprises the steps of (a) sampling the video signal by a plurality of dot clock signals that are expected to have different phase relationships to the video signal, thereby obtaining plural sets of image data; (b) carrying out a prescribed operation for each set of image data to obtain a phase-related index representing the phase relationship of the each set of image data, and determining a desirable phase for the dot clock signal based on the phase-related indexes of the plural sets of image data; and (c) applying an optimum delay to the dot clock signal to have the desirable phase.
Since the phase-related index indicates whether the phase relationship between the dot clock signal and the video signal is appropriate or not, a desirable phase can be determined on the basis of the phase-related index. The delay of the dot clock can be adjusted so that the dot clock has the desirable phase accordingly.
According to one embodiment of the present invention, the step (a) comprises the step of: applying a plurality of different delays to a reference clock to generate the plurality of dot clock signals, and sampling the video signal by each dot clock signal to obtain the plural sets of image data respectively representing images at an identical position on a screen; and
wherein the step (b) comprises the steps of: (1) calculating values of a function representing sharpness of the plural sets of image data as the phase-related indexes corresponding to the plurality of delays; (2) determining an extreme of the values of the function against the plurality of delays; and (3) selecting a delay among the plurality of delays as the optimum delay to attain the desirable phase, the selected delay corresponding to the extreme of the values of the function.
Whether the phase relationship between the video signal and the dot clock signal is appropriate or not can be judged on the basis of sharpness of the image data to be sampled by the dot clock. Therefore, a value of a function representing sharpness of image data may be used as the phase-related index. The value of the function will become different for a plurality of dot clock signals which are generated by different delay times and which have different phase relationship with the video signal accordingly. Further, the value of the function should have a maximum at a specific delay corresponding to a desired phase relationship. An appropriate delay for attaining the desirable phase relationship can be obtained by determining a maximum of the value of the function.
In another preferred embodiment of the present invention, the step (a) comprises the steps of: multiplying a frequency of a horizontal synchronizing signal of the video signal by a first factor to generate a first dot clock signal, the first factor being different from an appropriate second factor that is to be used for multiplying the frequency of the horizontal synchronizing signal to generate the dot clock signal having the desirable phase, the first dot signal including a plurality of signal phases which can be considered as the plurality of dot signals; and sampling the video signal by the first dot clock signal to obtain first image data on a specific line of the screen. Further, the step (b) comprises the steps of: dividing the first image data into a plurality of first image data blocks; calculating values of the function representing sharpness of the plurality of first image data blocks as the phase-related indexes of the plurality of first image data blocks, respectively; determining the extreme of the values of the function with respect to the plurality of first image data blocks; and selecting a delay corresponding to a specific first image data block related to the extreme of the values of the function as the optimum delay to attain the desirable phase.
The image data sampled by the first dot clock signal will includes a portion whose phase matches with the video signal and other portion whose phase does not. A desirable delay can be determined from the value of the function representing sharpness for a plurality of image data blocks which are divided from the image data for at lease one line.
The present invention is also directed to an apparatus for adjusting a phase of a dot clock signal for a video signal. The apparatus comprises: sampling means for sampling the video signal by a plurality of dot clock signals that are expected to have different phase relationships to the video signal, thereby obtaining plural sets of image data; phase determining means for carrying out a prescribed operation for each set of image data to obtain a phase-related index representing the phase relationship of the each set of image data, and determining a desirable phase for the dot clock signal based on the phase-related indexes of the plural sets of image data; and delay setting means for applying an optimum delay to the dot clock signal to have the desirable phase.
The present invention is further directed to a method of adjusting a frequency of a dot clock signal for a video signal. The method comprises the steps of: (a) multiplying a frequency of a horizontal synchronizing signal of the video signal by a first factor to generate a first dot clock signal; (b) sampling the video signal by the first dot clock signal to obtain image data: (c) analyzing the image data to determine a first value representing a length of an effective signal area on one line of the image data; (d) carrying out an operation using the first value representing the length of the effective signal area and a known second value representing a true length of the effective signal area, thereby determining a desirable second factor; and (e) multiplying the frequency of the horizontal synchronizing signal by the second factor to generate a desirable second dot clock signal.
The first value of the effective signal area of the image data can be determined by analyzing the image data. If a true length of the effective signal area, or the second value, is known, a desirable second factor can be determined so that the effective signal area has the second value. The desirable second dot clock will be generated with the second factor.
The present invention is also directed to an apparatus for adjusting a frequency of a dot clock signal for a video signal. The apparatus comprises: dot clock generation means for multiplying a frequency of a horizontal synchronizing signal of the video signal by a first factor to generate a first dot clock signal; sampling means for sampling the video signal by the first dot clock signal to obtain image data; first operation means for analyzing the image data to determine a first value representing a length of an effective signal area on one line of the image data; second operation means for carrying out an operation using the first value representing the length of the effective signal area and a known second value representing a true length of the effective signal area, thereby determining a desirable second factor; and factor setting unit for setting the desirable second factor in the dot clock generation means and thereby enabling the dot clock generation means to multiply the frequency of the horizontal synchronizing signal by the second factor to generate a desirable second dot clock signal.
According to an aspect of the present invention, the method of adjusting a frequency of a dot clock signal for a video signal comprises the steps of: (a) multiplying a frequency of a horizontal synchronizing signal of the video signal by a first factor to generate a first dot clock signal; (b) sampling the video signal by the first dot clock signal to obtain image data; (c) obtaining a number of beats over one line of the image data; (d) correcting the first factor with the number of beats, thereby obtaining a desirable second factor; and (e) multiplying the frequency of the horizontal synchronizing signal by the second factor to generate a second dot clock signal that can be used to sample image data without beats.
Image data will include some beats if sampled by the first dot clock having a non-appropriate frequency. A desirable second factor can be obtained by measuring the number of beats over one line of the image data and by correcting the first factor with the number of beats. Using the second factor, the second dot clock signal will be generated to sample image data without any beats. It should be noted that the second dot clock signal can be used in various purposes other than sampling a video signal.
According to another aspect of the present invention, the apparatus for adjusting a frequency of a dot clock signal for a video signal comprises: dot clock generation means for multiplying a frequency of a horizontal synchronizing signal of the video signal by a first factor to generate a first dot clock signal; sampling means for sampling the video signal by the first dot clock signal to obtain image data; first operation means for obtaining a number of beats over one line of the image data; second operation means for correcting the first factor with the number of beats, thereby obtaining a desirable second factor; and factor setting means for setting the second factor in the dot clock generation means and thereby enabling the dot clock generation means to multiply the frequency of the horizontal synchronizing signal by the second factor to generate a second dot clock signal that can be used to sample image data without beats.
The present invention is further directed to a dot clock regeneration circuit for regenerating a dot clock signal to be supplied to a sampling circuit for sampling a video signal. The dot clock regeneration circuit comprises: a PLL circuit for multiplying a frequency of a horizontal synchronizing signal of the video signal by a predetermined factor to generate a reference clock signal; a delay circuit for delaying the reference clock signal by a predetermined time to generate the dot clock signal; memory means for storing at least one line of image data supplied from the sampling circuit; and delay time setting means for controlling a writing process of the image data into the memory means, reading one line of the image data stored in the memory means to carry out a prescribed operation, and setting a delay time in the delay circuit based on the result of the prescribed operation to attain a desirable phase relationship between the video signal and the dot clock signal.
The present invention is further directed to a video signal display apparatus. The video signal display apparatus comprises: sampling means for sampling a video signal; clock generation means for multiplying a horizontal synchronizing signal by a predetermined frequency division factor to generate a dot clock; driving means for processing an output of the sampling means; a display device for displaying an image in response to an output of the driving means; display timing means for controlling a display timing of the display device; memory means for storing one line of data output from the sampling means; write timing means for outputting a write enable signal to the memory means; and control means for outputting a write arm signal to the write timing means to cause the memory means to store data of a specific line, reading out the data of the specific line stored in the memory means, carrying out a prescribed operation, and setting a factor in the clock generation means based on the result of the prescribed operation.
The present invention is also directed to a method of regenerating a dot clock in a video signal display apparatus. The method comprises the steps of: setting a provisional factor in the PLL circuit and storing data into the memory means; comparing a difference between the data read out of the memory means at adjoining addresses with a predetermined threshold value to determine a starting address and a terminal address of an effective signal area of the video signal stored in the memory means; determining a number of dot clocks corresponding to one line of the video signal from a difference between the starting address and the terminal address and the provisional factor; and setting the number of dot clocks as the frequency division factor in the clock generation means.
According to an aspect of the present invention, the method of regenerating a dot clock signal comprises the steps of: processing the data read out from the memory means with a high-pass filter; carrying out a non-linear operation and subsequently performing fast Fourier transform on the data after the high-pass filter processing; obtaining a peak in the result of the fast Fourier transform to determine a frequency of a beat component; and setting a factor in the clock generation means so that a frequency of the beat component becomes equal to zero.
According to another aspect of the present invention, the method of regenerating a dot clock signal comprises the steps of: processing the data read out from the memory means with a high-pass filter; carrying out a non-linear operation on the data after the high-pass filter processing and subsequently performing an operation with a plurality of comb filters; determining a frequency of a beat component based on a combination of integral values of the result of the operation with the plurality of comb filters; and setting a factor in the clock generation means so that a frequency of the beat component becomes equal to zero.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with the accompanying drawings.